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KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 1 ver. 1.1 preliminary general description the kawasaki KL5KUSB121 controller is a unique single chip solution to interface peripheral devices to the universal serial bus (usb) and ethernet. the KL5KUSB121 has been specifically designed to provide a simple solution to communicate with ethernet applications as well as other usb peripheral devices. this has been accomplished by its highly integrated functionality. the usb controller consists of a central 16-bit processor, mask rom, ram buffer, clock generator, ethernet interface, uart, irq, watchdog timer, serial interface, external memory interface and sport interface. the sie (serial interface engine) is fully compatible with the usb specification. our powerful internal processor enables remote ndis (network drive) which gives compatibility with next generation operating systems and faster data transfer. this usb to ethernet controller is ideal for lan (local area network), han (home area network), cable modem, set top boxes, or mobile networking applications. features advanced 16 bit processor for usb transaction processing and control data processing 10/100base-t compatibility usb interface ver. 1.0/1.1 compliant transceivers and sie (serial interface engine) internal clock generation - utilizes low cost external 12mhz crystal circuitry mii physical layer interface 1.5k x 16 internal ram buffer remote ndis for faster data transfer. fully ieee 802.3 compliant 10 mbit/sec ethernet mac layer. interfaces serially of an external endec phy. uart external memory interface lqfp package serial interface for external eeprom block diagram ram (3kb) timer 0 usb interface 16 bit address / data bus data - data + serial interface engine mask rom (8kb) timer 1 watchdog timer 16 bit processor uart txd rxd 10/100 mb/s ethernet interface mii phy interface eeprom serial interface dio ck sram interface a15-0 d15-0 cntrl . x2 x1 clock gen. & internal pll irq int 1-0 2
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 2 ver. 1.1 preliminary KL5KUSB121 application block diagram pin diagram 100lqfp vdd gnd vco_in cp_out pllen vdd n/c phrxd1 phrxd2 phrxd3 phrxer phrxdv gnd phtxd0 phcol phtxen phtxd1 phtxd2 phtxd3 phtxer gnd txd ugnd vp vm uvdd n/c n/c phtclk phrxclk phcrs ph_rxd0 x_pclk rxd irq0 irq1 dxa tsca fs vdd serromd serromclk pu#1 pclk dra gnd clk x2 xa_15 vdd xa_7 xa_6 xa_5 xa_4 xa_3 xa_2 xa_1 ntst nreset nxromsel nxwr nxrd gnd npdn gnd vdd n/c n/c led_on nxramsel ignd nxbhe xa_0 xa_14 ovdd vdd xd_15 xd_14 ognd xd_13 xd_12 ignd xd_11 xd_10 xd_9 xd_8 xd_7 xd_6 xd_5 xd_4 xd_3 xd_2 xd_1 xd_0 xa_13 xa_12 xa_11 xa_10 xa_9 xa_8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 KL5KUSB121_l optional external memory serial eeprom KL5KUSB121 usb / ethernet phy transformer usb full duplex 10/100 base ? t ethernet mii interface
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 3 ver. 1.1 preliminary pin description pin # lqfp i/o pin name description 1 in vdd vdd 2 gnd gnd pll gnd 3 in vco_in pll vco in 4 out cp_out pll vco out 5 in pllen pll enable 6 in vdd pll vdd 7 n/c n/c open connection 8 in phrxd1 phy receive data 1 9 in phrxd2 phy receive data 2 10 in phrxd3 phy receive data 3 11 in phrxer receive data error from phy 12 in phrxdv receive data valid from phy 13 in gnd ground 14 out phtxd0 transmit data to phy 15 in phcol collision input from phy 16 out phtxen transmit enable to phy 17 out phtxd1 transmit data 1 to phy 18 out phtxd2 transmit data 2 to phy 19 out phtxd3 transmit data 3 to phy 20 out phtxer transmit error to phy 21 in gnd ground 22 in/out txd uart txd 23 in ugnd usb gnd 24 in/out vp usb + pin 25 in/out vm usb ? pin 26 in uvdd usb vdd 27 nc nc open connection 28 nc nc open connection 29 in phtxclk phy transmit clock 30 in phrxclk phy receive clock 31 in phcrs phy carrier sense 32 in ph_rxd0 phy serial receive data 33 in/out x_pclk external pclk 34 in/out rxd uart rxd 35 in irq0 edge sens. interrupt 36 in irq1 edge sens. interrupt 37 out dxa sport mode or gpio7 38 in tsca sport mode or gpio8 39 in/out fs sport mode or gpio9 40 in vdd open connection 41 in/out serromd serial rom data 42 out serromclk serial rom clock 43 in/out pu#1 pull up to usb + pin for high speed 44 in pclk sport mode or gpio5 45 in dra sport mode or gpio6 46 in ognd gnd 47 in clk 12mhz clock/crystal input
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 4 ver. 1.1 preliminary pin # lqfp i/o pin name description 48 out x2 12mhz crystal output 49 out xa_15 external address pin 50 in vdd vdd 51 in ovdd vdd 52 out xa_14 external address pin 53 out xa_0 external address pin 54 out nxbhe sram byte high enable 55 in ignd gnd 56 out nxramsel sram byte low enable 57 out led_on turns on 3.3v to tx led 58 n/c n/c open connection 59 n/c n/c open connection 60 in vdd vdd 61 in gnd ground 62 in/out npdn active low powerdown mode signal to phy 63 in gnd gnd 64 out nxrd external memory read (active low) 65 out nxwr external memory write (active low) 66 n/c nxromsel external rom cs, active lo 67 in nreset reset pin 68 in ntst test pin, disconnect for normal operation 69 out xa_1 external address pins 70 out xa_2 external address pins 71 out xa_3 external address pins 72 out xa_4 external address pins 73 out xa_5 external address pins 74 out xa_6 external address pins 75 out xa_7 external address pins 76 out xa_8 external address pins 77 out xa_9 external address pins 78 out xa_10 external address pins 79 out xa_11 external address pins 80 out xa_12 external address pins 81 out xa_13 external address pins 82 in/out xd_0 external data pins 83 in/out xd_1 external data pins 84 in/out xd_2 external data pins 85 in/out xd_3 external data pins 86 in/out xd_4 external data pins 87 in/out xd_5 external data pins 88 in/out xd_6 external data pins 89 in/out xd_7 external data pins 90 in/out xd_8 external data pins 91 in/out xd_9 external data pins 92 in/out xd_10 external data pins 93 in/out xd_11 external data pins 94 in ignd gnd 95 in/out xd_12 external data pins 96 in/out xd_13 external data pins 97 in ognd gnd
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 5 ver. 1.1 preliminary pin # lqfp i/o pin name description 98 in/out xd_14 external data pins 99 in/out xd_15 external data pins 100 in vdd vdd function description 16 bit processor the integrated 16 bit processor serves as a micro controller for usb peripherals. the processor can execute approximately five million instructions per second. with this processing power it allows the design of intelligent peripherals that can process data prior to passing it on to the host pc, thus improving overall performance of the system. the masked rom (4k x 16) in the KL5KUSB121 or external memory contains a specialized instruction set that has been designed for highly efficient coding of processing algorithms and usb transaction processing. the 16-bit processor is designed for efficient data execution by having direct access to the ram buffer, external memory, i/o interfaces, and all the control and status registers. the divide/multiply feature expands the capability of usb peripherals. the processor supports prioritized vectored hardware interrupts. in addition, as many as 240 software interrupt vectors are available. the processor provides six addressing modes, supporting memory-to-memory, memory- to-register, register-to-register, immediate-to-register or immediate-to-memory operations. register, direct, immediate, indirect, and indirect indexed addressing modes are supported. in addition, there is an auto-increment mode in which a register, used as an address pointer is automatically incremented after each use, making repetitive operations more efficient both from a programming and a performance standpoint. the processor features a full set of program control, logical, and integer arithmetic instructions. all instructions are sixteen bits wide, although some instructions require operands, which may occupy another one or two words. several special ? short immediate? instructions are available, so that certain frequently used operations with small constant operand will fit into a 16-bit instruction. ram buffer the usb controller contains a 3k byte (1.5k x 16) internal buffer memory. the memory is used to buffer data and usb packets and accessed by the 16 bit processor and the sie. usb transactions are automatically routed to the memory buffer. the 16-bit processor has the ability to set up pointers and block sizes in buffer memory for usb transactions. data is read from the interface and is processed and packetized by the 16- bit i/o processor.
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 6 ver. 1.1 preliminary pll clock generator the pll circuitry is provided to generate the internal 48mhz clock requirements. this circuitry is designed to allow use of a low cost 12 mhz external crystal which is connected to the usb3 pins x1 and x2. if an external 12 mhz clock is available in the application, it may be used in lieu of the crystal circuit and connected directly to the x1 input pin. usb interface the usb controller meets the universal serial bus (usb) specification ver 1.0. the transceiver is capable of transmitting and receiving serial data at the usb?s full speed, 12 mbits/sec data rate. the driver portion of the transceiver is differential, while the receive section is comprised of a differential receiver and two single ended receivers. internally, the transceiver interfaces to the sie logic. externally, the transceiver connects to the physical layer of the usb. 10mb, 100mb/sec ethernet interface the KL5KUSB121 controller has a built in the ethernet mac (media access controller) which is fully compliant with the ieee 802.3 ethernet standard. the KL5KUSB121 connects externally to a 10 base -t and/or 100 base-t endec phy. the KL5KUSB121 controller 16-bit processor has direct access to the registers of the mac. uart interface supports a transfer rate of 900 to 115.2k baud. serial eeprom support the usb controller serial interface is used to provide access to external eeprom?s. the interface can support a variety of serial eeprom formats. sram interface an address port and 16-bit data port has been provided to interface to an external sram.
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 7 ver. 1.1 preliminary dc characteristics u2e is implemented with kawasaki ? s 0.5um cmos cba and embedded memory kz300em technology. the followings are the description of chip electric characteristics. 1 . absolute maximum ratings table 5.1 absolute maximum ratings parameter symbol ratings unit supply voltage vdd ? 0.3 ~ 4.0 v input voltage vin ? 0.3 ~ 7.3 v dc output current iout 15 ma storage temperature tstg ? 55 ~ 125 c
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 8 ver. 1.1 preliminary 2. recommended operating conditions table 5.2 recommended operating conditions parameter symbol min typ max unit operating supply voltage vdd 3.0 ? 3.6 v operating ambient temperature ta 0 ? 70 c 3. i/o electrical dc characteristics (over recommended range) table 3.1 dc characteristics (over recommended range) parameter symbol min typ max unit test conditions input low voltage vil ? ? 0.8 v input high voltage vih 2.0 ? ? v input low current iil ? 10 ? 10 ua vin = gnd input high current iih ? 10 ? 10 ua vin = vdd output low voltage vol ? ? 0.4 v iol = 4ma output high voltage voh 2.4 ? ? v ioh = ? 4ma 3-state leak current ioz ? 10 ? 10 ua voh = gnd or vol = vdd active pull-up current ipu ? 25 ? 66 ? 160 ua vin = gnd or voh = gnd standby current idds ? 80 100 ua vin = gnd or vdd no inputs are cycling. outputs open. suspend current isusp ? 350 450 ua same conditions as idds except for clki input buffer 48mhz toggling. iddop1 (in busy) ? 80 100 m a dynamic operating current iddop2 (in idle) ? 40 50 m a outputs open. vdd = max. fclki = fmax ( 48mhz ) input capacitance cin ? ? 15 pf output capacitance cout ? ? 15 pf fpin=1mhz, vin = gnd. vin = 100 mvrms
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 9 ver. 1.1 preliminary ac characteristics u2e chip has 4 types of interfaces ? usb port, ethernet phy port, sram port and serial eeprom port. ac timing of these interfaces are described below along with appropriate timing charts. chip also requires the ac timing of system clock input clki and system reset resetn. 1. clki and resetn signal figure 1 .1 clki and resetn ac t iming table 1 .1 clki ac c haracteristics (over recommended range) symbol parameter min typ max unit not e tpck clki one cycle time ? 20.83 ? ns 1 fck clki frequency ? 48 ? mh z 1 tckh clki high time 10 ? ? ns 1 tckl clki low time 10 ? ? ns 1 note: 1) the clock is used as an usb sampling clock and to generate the internal 32mhz clock pulse. table 1 . 2 resetn ac characteristics (over recommended range) symbol parameter min typ max unit not e tprst resetn low pulse width 10 ? ? tpc k 2 note: 2) resetn is an asynchronous , low assert , reset signal. minimum assertion is 10 times of tpck (210 ns). 2 . usb interface the usb signals ? vp and vm are the pair signals of the differential output driver and receiver. the usb to ethernet operates under usb full speed (12mb/s). usb signals are full y compatible with usb spec rev 1. 1 . tpck tckh tckl clki (in) tprst resetn (in)
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 10 ver. 1.1 preliminary 3 . phy interface u sb to ethernet exchanges the serial bit data and message s to the external phy chip . 3 .1 u2e to phy transmit figure 3.1.1 u sb to ethernet to phy transmit ac t iming table 3.1.1 phy t ransmit ac c haracteristics (over recommended range) symbol parameter min typ max unit not e ttck phytclk period ? 100 ? ns 1 ftck phytclk frequency ? 10 ? mh z 1 ttch phytclk high width ? 50 ? ns ? ttcl phytclk low width ? 50 ? ns ? tden1 phyten assert delay from phytclk rise ? ? 30 ns 2 tden2 phyten negate delay from phytclk fall 0 ? ? ns 2 tdtd1 phytxd valid delay from phytclk rise ? ? 28 ns 2 tdtd2 phyten valid delay from phytclk fall 0 ? ? ns 2 note: 1) phy generates the 10mhz clock. 2) 30pf capacitor external load is assumed. figure 3.1.2 phy sqe function ac t iming at transmit phyten (out) phycol (in) tcol tpco last phyten (out) phytxd (out) first phytclk (in) ttch ttck tden1 tdtd1 tden2 tdtd2 ttcl 98.09.02 updated
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 11 ver. 1.1 preliminary table 3.1.2 phy sqe t ransmit ac c haracteristics (over recommended range) symbol parameter min typ max unit not e tcol phycol assert delay from phyten fall ? ? 1.6 us ? tpco phycol low width 0.5 ? ? us ? 3.2 u2e to phy receive figure 3.2.1 u 2e from phy r eceive ac t iming table 3.2.1 receive from phy ac c haracteristics (over recommended range) symbol parameter min typ max unit not e trck phyrclk period ? 100 ? ns 1 frck phyrclk frequency ? 10 ? mh z 1 trch phyrclk high width ? 50 ? ns ? trcl phyrclk low width ? 50 ? ns ? tscd phycd setup time to phyrclk rise 20 ? ? ns ? thcd phycd hold time from phytclk rise 10 ? ? ns ? tsrd phyrxd setup time to phyrclk fall 20 ? ? ns ? thrd phyrxd hold time from phyrclk fall 10 ? ? ns ? note: 1) phy generates the 10mhz clock. phycd (in) phyrxd (in) phyrclk (in) last first trch trck trcl tscd tsrd thrd thcd
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 12 ver. 1.1 preliminary 4 . sram interface 4.1 sram read access figure 4.1.1 sram read ac t iming table 4.1.1 sram read ac c haracteristics (over recommended range) symbol parameter min typ max unit not e trc sram read cycle 31.25 ? ? ns 1,2 frc sram read frequency ? ? 32 mh z 1,2 taa srama valid to sramd delay (address access) ? ? 17 ns 2 thad sramd hold time from sramd invalid 2 ? ? ns 2 tpoe sramoen low width 31.25 ? ? ns 2 toe sramoen assert to sramd delay ? ? 10 ns 2 thoe sramd hold time from sramoen rise 0 ? ? ns 2 tpcs sramcsn low width 31.25 ? ? ns 1,2 tacs sramcsn assert to sramd delay ? ? 17 ns 2 thcs sramd hold time from sramcsn rise 0 ? ? ns 2 note: 1) same as the usb to ethernet internal clock cycle time 1t (31.25 ns). 2) outputs are assumed to have 30pf external capacitive load. srama14-0 (out) thad valid trc valid don't care tpoe thoe toe tpcs thcs tacs taa sramwen (out) sramoen (out) sramcsn (out) sramd7-0 (in)
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 13 ver. 1.1 preliminary 4.2 sram write access figure 4.2.1 sram write ac t iming table 4.2.1 sram write ac c haracteristics (over recommended range) symbol parameter min typ max unit not e twc sram write cycle 31.25 ? ? ns 1,2 fwc sram write frequency ? ? 32 mh z 1,2 tdaw sramwen assert delay from srama valid 0 ? ? ns 2 tdwa srama invalid delay from sramwen negate 0 ? ? ns 2 tdcw sramwen assert delay from sramcsn assert 0 ? ? ns 2 tdwc sramcsn negate delay from sramwen negate 0 ? ? ns 2 tpwe sramwen low width 25 ? ? ns 2 tdrv sramd drive delay from sramwen assert 0 ? ? ns 2 tval sramd valid from sramwen assert ? ? 15 ns 2 tts sramd hold time from sramwen rise 0 ? ? ns 2 note: 1) same as the usb to ethernet internal clock cycle time 1t (31.25 ns). 2) outputs are assumed to have 30pf external capacitive load. srama14-0 (out) sramoen (out) sramcsn (out) sramwen (out) sramd7-0 (out) tdwa valid twc valid tpwe tts tdaw tdcw tdwc tval tdrv
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 14 ver. 1.1 preliminary 5. serial eeprom interface the usb to ethernet device communicates with the serial eeprom (sep) through i 2 c ? bus. 5.1 serial eeprom access start figure 5.1.1 sep a ccess s tart ac t iming table 5.1.1 sep a ccess s tart ac c haracteristics (over recommended range) symbol parameter min typ max unit not e tdckr( st) sepsda fall delay from sepscl rise 4.7 ? ? us 1 tdckf( st) sepscl fall delay from sepsda fall 4.0 ? ? us 1 note: 1) 30pf external capacitive load is assumed. 5.2 serial eeprom access stop figure 5.2.1 sep a ccess s top ac t iming table 5.2.1 sep access stop ac characteristics (over recommended range) symbol parameter min typ max unit not e tdckr( sp) sepsda rise delay from sepscl rise 4.0 ? ? us 1 note: 1) 30pf external capacitive load is assumed. sepscl (out) sepsda (out) tdckf(st) tdckr(st) sepscl (out) sepsda (out) tdckr(sp)
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 15 ver. 1.1 preliminary 5.3 serial eeprom read access figure 5.3.1 sep r ead a ccess ac t iming table 5.3.1 sep read access ac characteristics (over recommended range) symbol parameter min typ max unit not e tsd sepsda setup time from sepscl rise 20 ? ? ns 1 thd sepsda hold time from sepscl fall 0 ? ? ns 1 not e: 1) 30pf external capacitive load is assumed. 5.4 serial eeprom write access figure 5.4.1 sep w rite a ccess ac t iming table 5.4.1 sep w rite a ccess ac c haracteristics (over recommended range) symbol parameter min typ max unit not e tsck sepscl clock period 10 ? ? us 1 fsck sepscl frequency ? ? 100 khz 1 tpckl sepscl low width 4.7 ? ? us 1 tpckh sepscl high width 4.0 ? ? us 1 tdd sepsda valid delay from sepscl fall 2 ? 20 ns 1 note: 1) 30pf external capacitive load is assumed. sepscl (out) sepsda (out) valid tpckl tpckh tckf tdd sepscl (out) sepsda (in) valid tsd thd
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 16 ver. 1.1 preliminary 6. serial eeprom access timing serial eeprom b yte w rite, p age w rite, c ur r ent a ddress r ead, r andom r ead and s equential r ead timings are shown below . please refer to serial eeprom datasheet ([12] 3-b) for more detail. 6 .1 serial eeprom byte write figure 6. 1.1 sep b yte w rite timings 6.2 serial eeprom page write (up to 16 bytes) figure 6.2.1 sep p age w rite t imings 6.3 serial eeprom byte read from current address figure 6.3.1 sep b yte r ead t imings idle s t 1 0 1 0 1 b 2 b 1 b 0 control byte a k read data s p n k d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 0 (7) (6) (5) (4) (3) (2) (1) (0) (l) status sepscl (out) sepsda (i/o) idle status s t a k control a k w addrn a k dat n a k dat n+1 a k dat n+1 a k max n+15 s p idle (internal programming cycle) (l) (l) (l) (l) (l) (l) a k s t control n k control byte data idle s p a k a k d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 0 s t twr = max 10ms for internal wr operation (ack polling needed to start next tran) idle status s t 1 0 1 0 0 b 2 b 1 b 0 control byte a k a 3 a 2 a 1 word address a 7 a 6 a 5 a 4 a 0 (l) (l) (l) (h) (l) sepscl (out) sepsda (i/o)
KL5KUSB121 usb to 10/100 ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 17 ver. 1.1 preliminary 6.4 serial eeprom byte random read figure 6.4.1 sep b yte r andom r ead timings 6.5 serial eeprom sequential read (up to final address) figure 6.5.1 sep s equential r ead t imings february 22, 2000 copyright 2000 kawasaki lsi printed in u.s.a kawasaki lsi assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. there are no warranties extended or granted by this document. the information herein is subject to change without notice form kawasaki lsi s t a k cntrl r idle s t a k cntrl w a k w addrn input input dat n+1 last in s p (l) (l) (l) l a k (dat n) (dat n+1) l a k l a k h n k status a k idle s t 1 0 1 0 0 b 2 b 1 b 0 control byte a k a 3 a 2 a 1 word address a 7 a 6 a 5 a 4 a 0 (l) (l) s t 1 0 1 0 1 b 2 b 1 b 0 control byte a k read data s p n k d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 0 (7) (6) (5) (4) (3) (2) (1) (0) (l) status sepscl (out) sepsda (i/o)

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